Senior Digital Physical Design Engineer

Senior Digital Physical Design Engineer
Location- Humburg
Necessary year of experience - 10 years plus
Duration of the contract - 10 Months
Job Description:
We are seeking a highly experienced Digital Physical Design Engineer with 10+ years of hands-on expertise in full-chip and block-level implementation. The candidate will be responsible for end-to-end physical design, including floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and sign-off.

Key Responsibilities:

• Perform complete P&R flow: floorplanning, power planning, placement, CTS, routing, and physical optimization
• Drive timing closure across all corners using advanced Static Timing Analysis (STA) techniques
• Execute and debug physical verification flows including DRC, LVS, and ERC using Calibre
• Analyze and fix timing, SI, IR drop, and EM issues
• Collaborate with RTL, DFT, PD, and verification teams to achieve design closure
• Ensure high-quality sign-off meeting PPA (Power, Performance, Area) targets

Requirements

• 10+ years of industry experience in digital physical design
• Strong expertise in both Cadence (Innovus, Tempus) and Synopsys (ICC2, PrimeTime) toolchains
• Proven proficiency in Calibre for physical verification and sign-off
• Deep knowledge of STA concepts, timing constraints, and closure methodologies
• Experience with advanced nodes and low-power design techniques is highly desirable

Preferred:

• Experience in both full-chip and subsystem integrations and tape-out cycles
• Scripting skills (TCL, Python) for flow automation
• Nice to have: previous experience with NXP projects

This role requires a self-driven engineer capable of handling complex SoC designs and delivering robust, sign-off quality results.