Senior Front-End RTL Digital Design Engineer

Senior Front-End RTL Digital Design Engineer

Job Description:
We are seeking a skilled Front-End RTL Design Engineer with 10+ years of experience in digital design and SoC development. The role involves RTL design, subsystem/SoC integration, and ensuring high-quality design implementation through rigorous verification and sign-off checks.

Key Responsibilities:

• Perform subsystem and full SoC integration, ensuring interface and architectural consistency
• Execute and analyze Lint, CDC, and RDC checks to ensure robust design quality
• Develop RTL for complex digital blocks and subsystems
• Support synthesis flows and optimize designs for timing, area, and power
• Participate in simulation, debugging, and functional verification activities
• Collaborate closely with verification teams with working knowledge of UVM-based methodologies
• Contribute to design reviews, architecture discussions, and quality sign-off processes

Requirements

• 10+ years of experience in RTL design and SoC/subsystem integration
• Strong knowledge of digital design fundamentals and micro-architecture
• Proficiency in synthesis tools (e.g., Synopsys Design Compiler or Cadence Genus)
• Hands-on experience with Lint, CDC, and RDC analysis and closure
• Solid understanding of simulation and digital verification concepts, including UVM
• Good scripting skills (TCL/Python) for automation

Nice to Have:

• Experience with SoC integration using Magillem tools (very nice to have)
• Interest or experience in applying AI/LLMs (e.g., Claude, Opus) to improve design flows, productivity, and methodology innovation (very nice to have)

This role suits a proactive engineer capable of driving design quality and integration in complex SoC environments while contributing to continuous improvement of design methodologies.